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AMIS-30522 micro-stepping motor driver data sheet 1.0 introduction t he AMIS-30522 is a micr o-stepping stepper motor driver for bipolar stepper m o to rs. t he chip is c onnec ted through i/o pins and a s p i interface w i t h a n e x tern al micr ocontro ller. it has an o n -chi p v o ltag e reg u lat o r, reset-output and w a tchd og reset, abl e to supp l y per iph e r a l devic es. amis-305 22 cont ain s a current-trans lati on tabl e and takes the ne xt micro-ste p dep end in g o n the clock sig nal o n the ?nx t? inp u t pin an d the status of th e ?dir? (= dire c t ion) re gister or inp u t pin. t he chip provi des a so-call ed ?s pe ed a nd l o a d a n g le? output. t h is allo w s the cre a tion of stal l d e tection al g o rit h ms and c ontr o l lo ops b a se d on l oad- an gl e to adj ust torque a nd sp ee d. it is using a propri e tar y pw m algorit hm for relia ble curr en t control. t he amis-305 22 is imp l em en ted i n i2t 100 t e chn o lo g y , e n a b lin g both hi gh -voltag e a nal o g circu i tr y an d digit a l fu nctio n a lit y o n th e same chip. t he chip i s full y com pati b le w i t h the aut omotive vo ltag e requ ireme n ts. t he AMIS-30522 is id ea ll y s u ited for g e n e ral-p u rpos e ste pper motor ap plicati ons i n th e autom otive, i ndustri a l, med i cal, and m a r in e envir onme n t. w i th the on-chi p voltag e reg u l a tor it further reduc es the bom for mechat ro nic stepp er ap plicati ons. 2.0 key features ? dual h-br id ge for 2-phas e ste pper motors ? programm abl e peak-curr ent u p to 1.6a usin g a 5-bit current dac ? on-chip curr en t translator ? spi interface ? spee d an d loa d ang le o u tput ? seven step m o des from full step up to 3 2 mi cro-steps ? f u ll y inte grate d current-se n s e ? pw m current control w i t h auto m atic selecti o n of fast and slo w d e ca y ? lo w emc pw m w i th se lecta b le vo ltag e slo pes ? active fly - back diodes ? f u ll outp u t prot ection a nd d i ag nosis ? t hermal w a r n i ng an d shutd o w n ? comp atibl e w i t h 5v and 3.3v microcontr o ll er s ? integrated 5v regu lator to sup p l y e x tern al mi crocontro ller ? integrated r e se t function to reset exter nal mi crocontro ller ? integrated w a t c hdo g functio n 3.0 ordering information table 1: orde ring information part no. package peak curre nt tem p . ra nge orderi ng c ode tube s orderi ng c ode tapes AMIS-30522 an a nqfp -32 (7 x 7 mm) 1600ma -40c ? ..125 c 0c522-0 01-x t d 0c522-0 01-x t p 1 a m i se m i co nd uc t o r ? june 2 007 , m-20684 -001 www.amis.com
AMIS-30522 micro-stepping motor driver data sheet 4.0 block diagram te m p . sen s e spi ot p timebas e po r di do cs cl k nx t sl a dir er r b a nd- gap loa d angle AMIS-30522 l ogic & re gist er s cha r gep ump t r a n s l a t o r vreg cl r pc 2 0 0 703 22 . 2 vb b p w m i - s ens e emc p w m i - s ens e emc vd d gn d mo t x p mo t x n mo t y p mo t y n cp n c p p vc p por/wd f i gure 1: b l ock diagram a m i s - 3052 2 5.0 pin description table 2: pin list and description name pin descrip tion do 31 spi data output vdd 32 logic supply o u t put (needs e x te r nal decoupling capacitor) gnd 1 grou nd, heat sin k di 2 spi data in clk 3 spi clock input nxt 4 next micro-step input dir 5 direction input errb 6 error o u tput sla 7 speed load angl e output cpn 9 negative connection of charge pu mp capacitor cpp 10 positive connect i on of charge p u m p capacitor vcp 11 charge p u mp filter-capacitor clr 12 ?clear? = chip r e set input csb 13 spi chip select in put vbb 14 high voltage supply input mot y p 15, 16 negative end of phase y coil outp u t gnd 17, 18 grou nd, heat sin k mot y n 19, 20 positive end of phase y coil outpu t motxn 21, 22 positive end of phase x coil output gnd 23, 24 grou nd, heat sin k mo txp 25, 26 negative end of phase x coil output vbb 27 high voltage supply inp u t / 8, 30 no function (to b e left open in nor mal operation) porb/wd 28 power-o n-r e set ( p or)a nd w a tchd og reset output tst o 29 test pin input (to be tied to grou n d in normal oper ation) 2 a m i se m i co nd uc t o r ? june 2 007 , m-20684 -001 www.amis.com
AMIS-30522 micro-stepping motor driver data sheet 1 2 3 5 4 6 7 8 24 23 22 20 21 19 18 17 9 1 01 1 1 21 3 1 4 1 5 1 6 32 31 30 2 9 28 27 26 25 do di cp n mo txp gnd g nd mot x p mo t y n po r/ wd mot y p clk vd d cl r cs di r nx t sla AMIS-30522 pc 20 070 309 . 2 gn d gnd gnd mo t y n mo t x n mo t x n mot y p vbb tst o cpp vcp vbb er r f i gure 2: p i n out a m i s - 30522 5.1 pack ag e t h e rmal ch ara c ter i stics t he nqf p is d e sig ned to pr o v ide su peri o r thermal perfor m ance, an d us ing a n e x p o se d die pad on the bottom surf ace of the p a c k ag e partly contribut e s to t h is. in or der to take ful l adva n tag e of this th ermal p e r f ormance, th e pcb must hav e feat ures to c ond uct h e a t aw ay from the p a cka ge. a therm a l grou nde d p a d w i t h therm a l v i a?s ca n ac hi ev e this. w i th a l a yout as sh o w n in f i gur e 3: pcb groun d p l an e la yo ut con d iti on, the therma l resist ance j u n c tion ? to ? am bie n t can be br oug ht do w n to a leve l of 30c/ w . figure 3: pcb gr ound plane layout condition nqfp-3 2 p c 20041128.2 3 a m i se m i co nd uc t o r ? june 2 007 , m-20684 -001 www.amis.com
AMIS-30522 micro-stepping motor driver data sheet 6.0 electrical specification 6.1 a b so lu te maxi mu m ratin g s stresses abov e those list ed i n t able 3 ma y cause imm edi a t e and p e rma n ent devic e fail u r e. it is not implied th at more that one o f these cond itions c an be ap pli ed sim u ltan eo usl y . table 3: absolut e maximum rati ngs sy mbo l parameter min. max. units v bb analog dc suppl y voltage (1 ) -0.3 +40 v ts trg storage temp era t ure -55 +160 c tamb ambient tempera t ure unde r bias -50 +150 c v esd electrostatic discharges on comp onent level (2 ) -2 +2 kv notes: (1) for limited time <0 .5s. (2) human body model (100pf v i a 1.5 k ? , according to jede c e i a- jesd22-a 1 14-b). 6 . 2 re c o mme nd ope r a t ion co nditi ons operatin g ran g e s defin e the li mits for functi onal o perati on a nd par ametric character i sti cs of the devic e. no te that the functi o nal it y of the chip outsi de th ese o per ating r ang es is not g uara n tee d . operatin g o u tside the rec o mme n ded op eratin g rang es for e x te nde d p e rio d s of time may affect device reliabilit y . table 4: operati ng ranges sy mbo l parameter min. max. units v bb analog dc suppl y +6 +30 v v dd logic supply o u t put voltage (1 ) 4 . 7 5 5 . 2 5 v iddd d y namic curre nt of vdd pin (inte r nal and exte rnal loads) (2 ) 18 ma t a ambient tempera t ure vbat d +18 -40 +125 c t a ambient tempera t ure vbat d +29 -40 +85 c t j junction tempera t ure +160 c notes: (1) voltage ou tpu t. (2) dy namic curren t i s w i th oscilla tor runni ng, all a nalog cell s activ e . all o u tpu t s u n loaded, no fl oatin g inpu ts. 4 a m i se m i co nd uc t o r ? june 2 007 , m-20684 -001 www.amis.com
AMIS-30522 micro-stepping motor driver data sheet 6 . 3 d c pa ra m e te rs t he dc p a ra meters ar e g i v en for v bb an d temp erature in t heir op era t ing r ang es un less other w i se spec ified. co nventi on: c u rre nts flo w in g in th e circuit are d e fin ed as pos itive. table 5: dc pa r a meters sy mbo l pin(s) parameter remark/ t est co nditi ons min. ty p . max. unit suppl y an d volt age re gula t or v bb nominal operatin g suppl y rang e 6 30 v i bb vbb total internal cur r ent consumption unloaded outpu t s 8 ma v dd regulated outp u t voltage 4.75 5 5.25 v i int internal load curr ent unloaded outpu t s 6v < v bb < 8v 20 i lo ad max. outp u t curr ent (e xternal an d internal loads) 8v < v bb < 30v 50 i ddlim curre nt limitation pin shorted to gr ound 150 ma i lo ad_ p d vdd output cu rrent in po w e r d o w n 1 po w e r-on-res e t (por ) v ddh internal por co mparato r thresho l d vdd rising 4.0 4.25 4.4 v v ddl vdd internal por co mparato r thresho l d vdd falling 3.68 v motor d ri v e r i mdm a x , peak max cur r ent th ro ugh motor coil in normal oper ation 1 6 0 0 m a i mdm a x , rms max rms cur r en t through coil in normal operation 800 ma i mdabs absolute error on coil current -10 10 % i mdr e l error o n c u rre nt r a ti o i c o ilx / i co il y -7 7 % v bb = 12v, t j = 2 7 c 0.45 0.56 ? r hs on- r esistance high-side driver, cur[4:0] = 0.. . 3 1 v bb = 12v, t j = 1 60 c 0.94 1.25 ? v bb = 12v, t j = 2 7 c 0.45 0.56 ? r ls 3 on- r esistance low-side driver, cur[4:0] = 2 3 ... 31 v bb = 12v, t j = 1 60 c 0.94 1.25 ? v bb = 12v, t j = 2 7 c 0.90 1.2 ? r ls 2 on- r esistance low-side driver, cur[4:0] = 1 6 ... 22 v bb = 12v, t j = 1 60 c 1.9 2.5 ? v bb = 12v, t j = 2 7 c 1.8 2.3 ? r ls 1 on- r esistance low-side driver, cur[4:0] = 9.. . 1 5 v bb = 12v, t j = 1 60 c 3.8 5.0 ? v bb = 12v, t j = 2 7 c 3.6 4.5 ? r ls 0 on- r esistance low-side driver, cur[4:0] = 0.. . 8 v bb = 12v, t j = 1 60 c 7.5 10 ? i mpd mo txp motxn moty p moty n pull-dow n curren t hiz mode 0.5 ma logi c inp u ts i leak input leakage (3 ) tj = 160 c 1 a v inl logic low thr e shold 1.5 v v inh di, clk nxt, dir clr, csb logic high threshold 3.5 v r pd clr tst0 internal pull-do wn resistor 120 300 k ? therm al w a rni n g an d shu t d o w n t tw thermal w a rning 138 145 152 c t ts d (1 ) (2 ) thermal shutdo w n t tw + 20 c charge p u m p 6v< v bb < 15v 2 * v bb ? 2.5 v v cp output voltage 15v < v bb < 3 0 v v bb + 1 2 . 5 v bb + 1 4 v bb + 1 5 . 5 v c b u ffe r vcp external buf fer c apacitor 180 220 470 nf c pum p cpp cpn external pu mp capacitor 180 220 470 nf notes: (1) no more than 100 cumula ted h our s in life time abov e tt w. (2) thermal shutdow n and low temper atur e w a rning are deriv ed from thermal w a rning. (3) n o t v a lid fo r pin s w i th in tern al pu ll-dow n re sis t or . 5 a m i se m i co nd uc t o r ? june 2 007 , m-20684 -001 www.amis.com
AMIS-30522 micro-stepping motor driver data sheet 6 . 4 a c pa ra m e te rs t he ac parameters are giv e n for v bb and te mperatur e in th eir op eratin g ra nges. table 6: ac pa ra meters sy mbo l pin(s) parameter remark/ t est co nditi ons min. ty p . max. unit intern al os cillator f os c freque nc y of int e rnal oscillator 3.6 4 4.4 mhz motor d ri v e r pwm frequenc y 2 0 . 8 2 2 . 8 2 4 . 8 k h z f pw m double pwm fre quenc y freque nc y dep e nds onl y on inter nal oscillator 41.6 45.6 49.6 khz f j pwm jitter frequ enc y tbd hz f d motxx pwm jitter depth tbd % f pw m emc[1:0] = 00 150 v/s emc[1:0] = 01 100 v/s emc[1:0] = 10 50 v/s tb ri se mot x x turn -on voltage slope, 10% to 90 % emc[1:0] = 11 25 v/s emc[1:0] = 00 150 v/s emc[1:0] = 01 100 v/s emc[1:0] = 10 50 v/s tb fa l l motxx turn -off voltage slope, 90% to 10 % emc[1:0] = 11 25 v/s digital o u tp uts t h2l do errb output fall-time from v inh to v in l capacitive load 400pf a nd pull- up resistor of 1.5 k ? 5 0 n s charge p u m p f cp cpn cpp charge p u mp fre quenc y 250 khz t cpu motxx start-up time of c harge pum p spec extern al components c l r fu nc t i on t clr clr hard r e set durati on time 20 90 s po w e r-up t pu power-u p ti me v bb =12v, i lo ad =5 0ma, c lo ad =22 0nf 1 1 0 s t pd p o w e r - dow n t i me external conditio n s tbd ms t po r r e s e t d u r a t i o n 1 0 0 m s t rf po rb/ wd reset filter time 1 s w a tchd og t wd t o watchdog time out interval 32 512 ms t wd p r prohibited w a tch dog ackno w ledg e dela y 2 ms t wd r d po rb/ wd watchdog reset dela y tbd s 6 . 5 spi timi ng table 7: spi timing paramete rs sy mbo l parameter min. ty p . max. unit t clk spi clock period 1 s t clk_ high spi clock high time 100 ns t clk_ lo w spi clock low tim e 100 ns t set _di di set up time, valid data before r i sing edge of cl k 50 ns t ho ld_di di hold time, hold data afte r rising edge of c l k 50 ns t csb _ high csb high time 2.5 s t set _cs b csb set up time, csb low b e fore rising edge of cl k 100 ns t set _cl k clk set up time, clk low befor e ri sing edge of cs b 100 ns 6 a m i se m i co nd uc t o r ? june 2 007 , m-20684 -001 www.amis.com
AMIS-30522 micro-stepping motor driver data sheet di va li d clk t set _ c sb p c 20070 608 . 1 cs t clk t clk_hi t clk _lo t set _ d i t ho l d _d i t set _ c l k 0, 2 v cc 0, 8 v cc 0, 2 v cc 0, 2 v cc 0, 2 v cc 0, 8 v cc f i gure 4: sp i timing 7.0 typical application schematic am is- 3 05 22 p c 200 70 604 . 1 0 vcp cpp cpn cl r c 7 gn d cl k di do nxt di r mo txp motx n moty p moty n m 220 nf 10 0 nf c 5 v ba t v d d vbb vb b 10 0 nf 220 nf 100 f c 2 c 3 c 6 c 1 100 nf 100 nf c 4 sla c 8 r 1 c d 1 po r / w d cs err f i gure 5: typical a pplication schem a tic a m i s - 30522 table 8: ext e rnal components list and description com p o n en t func tio n ty p . v a l u e tolera n ce unit c 1 v bb buf fer capaci t or (1 ) 100 -20 +80% f c 2 , c 3 v bb decou pling block capacitor 100 -20 +80% nf c 4 v dd buffer capaci t or 220 +/- 20 % nf c 5 v dd buffer capaci t or 100 +/- 20% nf c 6 charge -pump b u ffer capacitor 220 +/- 20% nf c 7 charge -pump p u m ping capacitor 220 +/- 20% nf c 8 lo w pass filter sla 1 +/- 20% nf r 1 lo w pass filter sla 5.6 +/- 1% k ? d 1 optional reverse protection diode e.g. 1n4003 notes: 1. low esr < 1ohm . 7 a m i se m i co nd uc t o r ? june 2 007 , m-20684 -001 www.amis.com
AMIS-30522 micro-stepping motor driver data sheet 8.0 functional description 8.1 h-bridge dri v ers a full h- brid ge is inte grate d for eac h of the t w o stator w i ndi ngs. eac h h-brid ge c onsi s ts of t w o lo w - side and t w o hig h -sid e n-t ype mosfet s w itc hes. writing lo gic ?0 ? in b i t < m ot en> disables a ll driv ers (high- impe da nce). w r iting l ogic ? 1 ? in th is bit ena bles bo th brid ges an d cu rrent can flo w i n the motor stator w i nd ings. in order to avoid lar ge curre nts through th e h-brid ge s w i t ches, it is guarantee d that t he top- a n d bot tom-s w i tc hes o f the s a me ha l f - brid ge are nev er cond uctive s i multa neo usl y ( i nterl o ck del a y ) . a t w o-sta ge protection aga in st shorts on m o to r lin es is im plem ented. in a first stage, the curre nt in t he driv er is l i mited. secondly, w hen ex cessive voltage is sensed across the transistor, the transistor is sw itched off. in order to re d u ce the ra di ate d /cond ucted e m ission, vo ltag e slop e co ntrol is impl ement e d in the outp u t s w itc hes. t he output sl o pe i s defin ed b y the gate-dr ain c a p a cit anc e of o u tput transistor a nd t he ( limite d ) current that dr ives the gate. t here are t w o trimmi ng bits for slop e control ( t able 27: spi contro l param e ter overvie w emc[1:0] ). t he po w e r tra n sistors are eq uip ped w i th so -calle d ?activ e dio des ?: w h en a current is for c ed trou gh the transistor s w it ch in the re v e rse directi on, i.e. from source to d r ain, t hen the transistor is s w it ched o n . t h is ensur es that most of the current flo w s thro ug h the chan nel of the transistor i n stead of thro u gh the in her ent par asitic dr ain - bulk d i od e of the transistor. dep end in g o n the d e sir ed c u rr ent ra nge an d t he micr o-step positi on at ha n d , the r d so n o f the lo w - sid e t r ansistors w i l l be a d a p t ed s u ch that e x ce lle nt current-se n se accurac y is m a inta ine d . t he rds o n of th e hi gh-s i de tra n sistors rem a i n u n cha n g ed, see t able 5: dc parameters for more details. 8 . 2 pwm curre nt control a pw m comp a r ator com pares conti nuo usl y t he actual w i nd i ng c u rrent w i th the r e q uested curre nt an d fe eds back t he i n formatio n to a digit a l reg u lati o n loo p . t h is loop then g e n e r a tes a pw m signa l, w h ich tur n s on/off the h-bridg e s w itch e s . t he s w itchi n g poi nts of the pw m dut y - c y cl e are s y nchr on ized to the o n - c hip pw m cloc k. t he fr equen c y of the pw m control l er can be do ub led a n d an artifici al jit ter can be a dde d ( t able 16: spi contro l reg i ster 1 ). t he pwm frequenc y w i ll not var y w i t h chan ges in the suppl y volta g e . also variatio n s in motor-s pe e d or l o a d -con ditio n s of the motor hav e n o effect. t here are no e x te rnal c o mpo n e n ts requ ire d to ad just the pw m freque nc y . 8.2.1. auto matic f o r w ard and sl ow -f ast decay t he pw m gen eratio n is in st ead y-state usi ng a comb in ation of for w ar d and slo w - d ec a y . t he a b se n c e of fast-dec a y in this m o d e , guar ante e s the lo w e st p o ssib l e curre nt-rip p le ?b y d e si gn?. f o r trans i ents to lo w e r c u rrent l e vels, fast-d ec a y is autom atic all y activated t o allo w hi gh-sp e ed resp onse. t he sel e ction of fast or slo w d e c a y is com p let e l y tra n sp arent for the user and no a dditi on al par amet ers are requ ired for o p e ratio n . ic o i l 0 t forwa r d & slo w dec a y for w a r d & s l ow de cay fast d e cay & for w a r d a c tu a l v a lu e set v a lue t pw m pc200 7060 4 . 1 f i gure 6: f o rward and slow/f ast decay pw m 8 a m i se m i co nd uc t o r ? june 2 007 , m-20684 -001 www.amis.com
AMIS-30522 micro-stepping motor driver data sheet 8.2.2. auto matic du ty cycle adaptation in case the su ppl y vo ltag e is lo w e r tha n 2* bemf, then the dut y c y cl e of the pw m is adapte d autom a t icall y to > 50% to maintai n th e requ ested aver age c u rrent i n t he co ils. t h is process is com p lete l y aut oma t ic and r equ ire s no a dditi on al param eters fo r oper ati on. t he over-al l curre nt-rippl e is div i de d b y t w o if pw m frequenc y is dou ble d ( t able 16: spi control re gister 1 ). actual value duty c ycl e < 50% duty cycl e > 50% d u ty cy cle < 50 % t ic o i l set valu e t pwm pc 20 0706 04 . 2 figure 7: automatic duty cycl e ada p tion 8.3 step t r an slato r 8.3.1. step mode t he step translator provi des the contro l of the motor b y m e ans of spi regi ster stepmode : sm[2:0 ], spi register dirc nt rl, and in pu t pins dir a nd n x t . it is translating cons ecutiv e steps in corr espo ndi ng curr ents in bot h motor coils for a give n step mod e . one o u t of s e ven possi bl e s t eppi ng m o d e s can be sel e ct ed thr oug h sp i-bits sm[2:0] ( t able 28: spi co ntrol p a ra meter overvi e w sm[2:0] ) after po w e r-on or h a r d reset, the c o il-curre nt transl a tor is set to th e defa u lt 1/3 2 micro-step pin g at positi on ?0? . u p on ch an gi ng the step m ode , the transl a tor jumps to pos i t ion 0 * of th e corresp ond in g steppi ng m ode . w hen rema i n in g in the s a me step mo de , subse q u ent translator p o sitio n s are all in the same colum n and i n creas ed or decre ased w i t h 1. t able 10 lists the outp u t current vs. the translator position. as sho w n in f i gur e 8 th e o u tput curre nt-pa i rs can b e pr oj ec ted a ppr o x i m atel y o n a c i rcle i n the (i x ,i y ) p l an e . t h e r e i s , h o w e ve r, one exc epti on: unc ompe nsate d h a lf st ep. in this step m ode th e curre nts ar e not re gul ated to a fr action of imax but are i n al l i n ter me di ate steps re gul ate d at 10 0 p e rce n t. in the (i x ,i y ) pl ane the curr ent-pa i rs ar e p r ojecte d o n a s quar e. t able 9 lists th e o u tpu t current vs. t h e translator position for this case. table 9: squa re translator table for uncompensat ed half step sm[ 2 :0] = 101 stepm o d e ( sm[ 2 :0] ) % of imax 101 unco mpe n sa te d half s t ep coil x coil y 0 * 0 100 1 1 0 0 1 0 0 2 100 0 3 1 0 0 - 1 0 0 4 0 -100 5 - 1 0 0 - 1 0 0 6 -100 0 7 - 1 0 0 1 0 0 9 a m i se m i co nd uc t o r ? june 2 007 , m-20684 -001 www.amis.com
AMIS-30522 micro-stepping motor driver data sheet table 10: circula r tra n slator tabl e stepm o d e ( sm[ 2 :0] ) % of imax stepm o d e ( sm[ 2 :0] ) % of imax 000 001 010 011 100 110 000 001 010 011 100 110 1/32 1/16 1/8 1/4 1/2 fs coil x coil y 1/32 1/16 1/8 1/4 1/2 fs coil x coil y ?0? 0 * 0 * 0 * 0 * - 0 100 64 32 16 8 4 - 0 -100 1 - - - - - 3.5 98.8 65 - - - - - -3.5 -98.8 2 1 - - - - 8.1 97.7 66 33 - - - - -8.1 -97.7 3 - - - - - 12.7 96.5 67 - - - - - -12.7 - 96.5 4 2 1 - - - 17.4 95.3 68 34 17 - - - -17.4 -95.3 5 - - - - - 22.1 94.1 69 - - - - - -22.1 - 94.1 6 3 - - - - 26.7 93 70 35 - - - - -26.7 -93 7 - - - - - 31.4 91.8 71 - - - - - -31.4 - 91.8 8 4 2 1 - - 34.9 89.5 72 36 18 9 - - -34.9 -89.5 9 - - - - - 38.3 87.2 73 - - - - - -38.3 - 87.2 10 5 - - - - 43 84.9 74 37 - - - - -43 -84.9 1 1 - - - - - 46.5 82.6 75 - - - - - -46.5 - 82.6 12 6 3 - - - 50 79 76 38 19 - - - -50 -79 1 3 - - - - - 54.6 75.5 77 - - - - - -54.6 - 75.5 14 7 - - - - 58.1 72.1 78 39 - - - - -58.1 -72.1 1 5 - - - - - 61.6 68.6 79 - - - - - -61.6 - 68.6 16 8 4 2 1 1 65.1 65.1 80 40 20 10 5 3 -65.1 -65.1 1 7 - - - - - 68.6 61.6 81 - - - - - -68.6 - 61.6 18 9 - - - - 72.1 58.1 82 41 - - - - -72.1 -58.1 1 9 - - - - - 75.5 54.6 83 - - - - - -75.5 - 54.6 20 10 5 - - - 79 50 84 42 21 - - - -79 -50 2 1 - - - - - 82.6 46.5 85 - - - - - -82.6 - 46.5 22 11 - - - - 84.9 43 86 43 - - - - -84.9 -43 2 3 - - - - - 87.2 38.3 87 - - - - - -87.2 - 38.3 24 12 6 3 - - 89.5 34.9 88 44 22 11 - - -89.5 -34.9 2 5 - - - - - 91.8 31.4 89 - - - - - -91.8 - 31.4 26 13 - - - - 93 26.7 90 45 - - - - -93 -26.7 2 7 - - - - - 94.1 22.1 91 - - - - - -94.1 - 22.1 28 14 7 - - - 95.3 17.4 92 46 23 - - - -95.3 -17.4 2 9 - - - - - 96.5 12.7 93 - - - - - -96.5 - 12.7 30 15 - - - - 97.7 8.1 94 47 - - - - -97.7 -8.1 3 1 - - - - - 98.8 3 .5 95 - - - - - -98.8 - 3.5 32 16 8 4 2 - 100 0 96 48 24 12 6 - -100 0 3 3 - - - - - 98.8 - 3.5 97 - - - - - -98.8 3 .5 34 17 - - - - 97.7 -8.1 98 49 - - - - -97.7 8.1 3 5 - - - - - 96.5 - 12.7 99 - - - - - -96.5 12.7 36 18 9 - - - 95.3 -17.4 100 50 25 - - - -95.3 17.4 3 7 - - - - - 94.1 - 22.1 101 - - - - - -94.1 22.1 38 19 - - - - 93 -26.7 102 51 - - - - -93 26.7 3 9 - - - - - 91.8 - 31.4 103 - - - - - -91.8 31.4 40 20 10 5 - - 89.5 -34.9 104 52 26 13 - - -89.5 34.9 4 1 - - - - - 87.2 - 38.3 105 - - - - - -87.2 38.3 42 21 - - - - 84.9 -43 106 53 - - - - -84.9 43 4 3 - - - - - 82.6 - 46.5 107 - - - - - -82.6 46.5 44 22 11 - - - 79 -50 108 54 27 - - - -79 50 4 5 - - - - - 75.5 - 54.6 109 - - - - - -75.5 54.6 46 23 - - - - 72.1 -58.1 110 55 - - - - -72.1 58.1 4 7 - - - - - 68.6 - 61.6 111 - - - - - -68.6 61.6 48 24 12 6 3 2 65.1 -65.1 112 56 28 14 7 0 * -65.1 65.1 4 9 - - - - - 61.6 - 68.6 113 - - - - - -61.6 68.6 50 25 - - - - 58.1 -72.1 114 57 - - - - -58.1 72.1 5 1 - - - - - 54.6 - 75.5 115 - - - - - -54.6 75.5 52 26 13 - - - 50 -79 116 58 29 - - - -50 79 5 3 - - - - - 46.5 - 82.6 117 - - - - - -46.5 82.6 54 27 - - - - 43 -84.9 118 59 - - - - -43 84.9 5 5 - - - - - 38.3 - 87.2 119 - - - - - -38.3 87.2 56 28 14 7 - - 34.9 -89.5 120 60 30 15 - - -34.9 89.5 5 7 - - - - - 31.4 - 91.8 121 - - - - - -31.4 91.8 58 29 - - - - 26.7 -93 122 61 - - - - -26.7 93 5 9 - - - - - 22.1 - 94.1 123 - - - - - -22.1 94.1 60 30 15 - - - 17.4 -95.3 124 62 31 - - - -17.4 95.3 6 1 - - - - - 12.7 - 96.5 125 - - - - - -12.7 96.5 62 31 - - - - 8.1 -97.7 126 63 - - - - -8.1 97.7 6 3 - - - - - 3.5 - 98.8 127 - - - - - -3.5 98.8 10 a m i se m i co nd uc t o r ? june 2 007 , m-20684 -001 www.amis.com
AMIS-30522 micro-stepping motor driver data sheet iy ix iy ix uncompens at ed h a l f st ep sm [ 2 :0 ] = 101 1/ 4 th m i cr o st ep sm[2 :0] = 011 st ep 1 st art = 0 pc 200 70604 .5 st e p 2 step 3 st a r t = 0 step 2 st ep 1 step 3 f i gure 8: translator table: circular and squ are 8.3.2. directio n t he direction of rotation is selecte d b y m eans of foll o w i ng co mb inati o n of the dir input pi n an d the spi-control l ed dir e ction b it . ( t able 16: spi contro l reg i ster 1 ) 8.3.3. nxt input cha nges on th e nxt input w ill move th e motor current o n e step up/ d o w n in the trans l a tor table. d e p end ing on the nxt - pol arit y bi t ( t able 16: spi control re gister 1 ), the ne xt step is initiat ed eit her on the risi ng e dge or the fa lli ng ed ge of the nxt input. dir nxt pc 20070609 . 1 vali d t nx t_hi t nxt _ lo t dir _ se t t di r _ hold 0, 5 v cc f i gure 9: nx t- input timing diagra m table 11: timing table nxt pin sy mbo l parameter min. ty p . max. unit t nx t _ hi nxt minimum, high pulse w i dth 2 s t nx t _lo nxt minimum, low p u lse w i dth 2 s t dir_s e t nxt hold time, f o llow i ng change of dir 500 s t dir_hold nxt hold time, b e fore change of dir 500 s 11 a m i se m i co nd uc t o r ? june 2 007 , m-20684 -001 www.amis.com
AMIS-30522 micro-stepping motor driver data sheet 8.3.4. t r anslator pos i tion t he translator positi on ca n b e rea d in t abl e 32: spi status reg i ster 3 . t h is is a 7-bit numb e r eq uiva lent to the 1/32 th micro-step fr om t able 10. t he transl a tor positi on is up date d i mmediat el y foll o w in g a n x t trigg e r. nx t up date tr an s l a t or p o s i t i on updat e trans l a tor p o sit i on pc20070604 .4 f i gure 10: transla tor p o sition timing diagram 8.3.5. synchro n i z a t i o n of step mode and nxt input w hen ste p mo de is re-pr ogr a mmed to an oth e r reso luti on ( t abl e 1 5 : spi c ontrol re gister 0 ), then this is put i n effect i mmediat el y up on the first arrivin g ?nxt ? input. if the micro-stepp ing res o luti on is incre a se d ( f i gure 11 ), then the coi l currents w i l l be regulat ed to the near est micro- step, accor d in g to the fi xed gri d of the incr ea s ed res o l u tion. if ho w e v e r the micro-step pin g resol u tio n is d e crea s ed, the n it is possi ble to i n troduc e an off s et (or phase s h ift) in the micr o-step transl a tor table. if the step r e so lutio n is decr e a s ed at a tra n sl ator tab l e posit i on t hat is s har ed both b y the old an d n e w r e soluti on s e tting , t hen th e offse t is zero an d mic r o-stepp ing is proce eds acc o rdin g to the translator tab l e. if the translato r positi on is no t shared both b y the old an d ne w res o luti on settin g , the n the micr o-stepp ing proc ee ds w i th an offse t relativ e to the transl a tor table (see f i gur e 10 right han d sid e ). ix dir iy ix iy di r nx t 1 nx t 2 nx t 3 nx t 4 ha lf s t e p end po s 1/4 th st ep c hange f r om l o w e r t o high er r e s o lut i on sta r t pos pc 20070604 . 6 iy ix iy ix dir nx t 1 nx t 2 nxt3 dir e n d pos ha lfste p 1/8 th st ep cha nge f r om hi gher t o l o we r r e so lut i on star t pos f i gure 11: nx t- step mode synchron ization left: change from lower to higher res o lu tion. the left-hand side depicts th e ending half-step position d u ring wh ich a new step mode resolution was p r o g rammed. the right-hand side dia g r a m shows the effect of subsequent nxt comm ands on th e micro-step position. right: change fro m higher to lower resoluti on. the left-hand side depicts the ending mi cro-step position du ring which a new ste p mode resolution was p r o g rammed. the right-hand side dia g r a m shows the effect of subsequent nxt commands on th e half-step position . note: i t i s adv is ed t o redu c e t h e m i cro-st eppi ng re s o lu t i on only at m i c r o- s t ep po s i t i o n s t h a t ov erlap w i t h desired m i c r o - st ep posit io ns of t h e ne w res o lut i on . 12 a m i se m i co nd uc t o r ? june 2 007 , m-20684 -001 www.amis.com
AMIS-30522 micro-stepping motor driver data sheet 8.4 pro g r amm a b l e peak- cu rren t t he amplitud e of the current w a v e form in the motor coil s (coil pe ak c u rrent = imax) is adjuste d b y me ans of a n spi paramet er "cur[4:0]" ( t able 15: spi co ntrol r egister 0 ). w henev er this p a rameter i s chan ged, th e coil-curr ents w i ll be upd ate d immed i ate l y at the ne xt pw m peri od. more in formation ca n be foun d in t able 2 6 : spi control param e te r overvie w cu r[4:0] . 8 . 5 spe e d a nd l o a d a ngle out put t he sla-pin provides an output voltage th at indicates the lev e l of the back-e.m.f. vo ltage of the m o tor. t h is back-e.m.f. volta ge i s sampl ed dur in g ever y so-ca l l ed "co il curre nt zero crossin g s ". per coil, t w o zero-curr ent positi ons e x ist per el ectrical p e rio d , y i e l di ng in total four zero- c urrent obs erv a tion p o i n ts pe r electrical peri od. v bem f zo o m t v bb v co i l voltag e t r a n sien t next m i cro - step pr e v io u s mi cro- st ep coil cu rren t zero cro ssi n g current deca y ze ro cu rre n t t t pc2 007 06 04 . 7 i co i l i co i l v bem f f i gure 12: p r inciple of b e mf measurement becaus e of the rel a tivel y hi gh recircu l ati o n c u rrents in t he c o il dur ing curr e n t dec a y , the c o il volta g e v coil sho w s a tran sient be havi o r. as this transie nt is not al w a ys desire d in ap plicati on s o ft w a re, t w o op erat ing mo des c a n be sel e cted b y me ans of the bit (see "sla-trans pare n c y " i n t able 1 7 : spi co ntrol regist er 2 ). t he sla pi n s h o w s in "tra nspar ent mo de" full visibi lit y of the voltag e tra n sie n t beh avior. t h is allo w s a san i t y -check of the spee d-settin g versus motor op eratio n an d ch aracteristics a n d supp l y v o ltag e leve ls. if the bit ?slat ? is clear ed, the n onl y t he v o ltag e s a mp les at the e nd of eac h c o il curre nt zero c r ossin g ar e vis i ble on the sla - pin. b e ca us e t h e transie nt be ha vior of the c o il voltag e is n o t visibl e a n y mor e , this mod e g ener ates smoo ther back e.m. f. input for post - processi ng, e. g. by soft w a re. in order to bring the sampled back e. m.f. to a descent output level (0 to 5v), t he sampled coil voltage v coil i s d i vi de d by 2 o r by 4 . th i s divid e r is set throug h an spi b i t . ( t a ble 1 7 : spi control re gister 2 ) table 12: par a m e ter ta ble sla pin sy mbo l pin(s) parameter remark/ t est co nditi ons min ty p max unit v out output voltage ra nge 0.5 4.5 v v of f output of fset the sla pin 0.2v < vsla < vdd ? 0.2v -20 20 mv r out output resistance sla pin 1 k ? c loa d load capacitance sla pin 50 pf g sl a sla gain of sla pin = v bemf / v coil slag =0 slag =1 0.5 0.25 13 a m i se m i co nd uc t o r ? june 2 007 , m-20684 -001 www.amis.com
AMIS-30522 micro-stepping motor driver data sheet t he follo w i n g d r a w in g il lustrat e s the op er ati o n of the sla-p i n and th e trans pare n c y -bi t. "pw m sh" and "i coil= 0" are int e rnal si gna ls tha t defin e togeth e r w i th s l at the sampli ng a nd h o ld mom ents o f the coil volta g e . pwm s h ico i l = 0 slat sl a - p i n sl at = 0 => sla-pin is no t "tr a nsp a ren t " d u ri n g v be m f s a mp li ng @ co il cu r r e n t z e ro cro s s i ng . sla-pin is up da ted wh en l e avi n g cu r r e n t - less sta t e. sl at = 1 = > sla - p i n i s "t r a n s pa r e nt " du r i ng v be mf s a m p lin g @ c o il c u rren t zero c r o ssi ng . s l a - pi n i s up da t e d " r e a l - t i m e " . la s t sa mp le is r e tained re ta in la st sa m p le pr ev i ous o u tput i s k ept at sla pi n buf ssh s h ch cs h slat n o t ( i c oi l = 0) ic oi l = 0 pwm s h sla - pi n v coi l di v 2 di v 4 v be m f t t pc 200 70604 .8 v co i l f i gure 13: timing diagram of sla - pin 8.6 warning, error detecti on and diagnostics feedback 8.6.1. t hermal w a rni ng an d shutd o w n w hen ju nctio n temperatur e rises ab ove t tw , the therma l w a rni ng b i t is set ( t abl e 29: spi status reg i ste r 0 ). if junction temperatur e i n creases ab ove thermal shut d o w n lev e l, the n the c i rcuit g oes i n ?t hermal sh utdo w n ? mode ( ) an d al l dr iver transistors are dis abl ed (hi g h im ped anc e) ( t able 31: s p i status r e g i ster 2 ). t he cond itions to r e set fla g i s t o b e a t a temperatur e lo w e r than t tw and to clear th e < tsd> flag b y r ead ing it us ing an y spi read c o mman d . 8.6.2. over-current detectio n t he over-curre nt detectio n cir c uit mon i tors the l oad c u rre nt in e a ch activ a t ed o u tput stag e. if the loa d c u rrent e x c e e d s the ov er-c urrent detectio n thres hol d, then the over-curre nt flag is set and the drivers are s w itc h e d off to reduc e th e po w e r d i ssip a tio n a nd to pr otect th e integr ated circuit. ea ch driv er trans istor has an i n d i vid ual detect i on bit in 14 a m i se m i co nd uc t o r ? june 2 007 , m-20684 -001 www.amis.com
AMIS-30522 micro-stepping motor driver data sheet t able 30: spi status reg i ste r 1 an d ( t able 31: spi status regist er 2 ( an d ). error con d itio n is latche d a nd th e microcontr o ll er needs to cl ean the status bits to reactivate th e drivers. 8.6.3. open co il det e ction open co il dete c tion is bas ed on the obs erva tion of 100 per cent dut y c y c l e of the pw m r egu lator. if in a coi l 1 00 perc ent dut y cy cl e is detected for l o nger t han 20 0 m s then th e r e late d dr iver tr ansistors are disa ble d (h igh- impe danc e) a n d an a ppro p ria t e bit i n the sp i status register i s set ( or ). ( t able 29: spi status register 0 ) 8.6.4. char ge pu mp f a ilure t he charge pu mp is an impor tant circuit that guara n tees lo w r d son for al l drivers, espec i a ll y for lo w su p p l y v o lta ges. if supp ly vo l t ag e is too lo w or e x ternal com p o n ents are n o t proper l y c o n nect ed to gu ara n te e rdso n of the drivers, then t he bit is set in ta b l e 29: spi status re gister 0 . al so after por t he c harg e pum p vo ltag e w i ll n eed some time to e x c e e d th e requ ired thres h old. duri ng tha t time w i ll be set to ?1?. 8.6.5. error output t h is is a d i gita l outp u t to fla g a pro b l e m to th e e x ter nal micr ocontro ller. t he sig n a l o n this outp u t is activ e lo w a nd t he l o g ic c o mb inati o n of: not ( errb) = or or or < ov cyij> or or 8 . 7 logic s upp ly re gula t or amis-3052 2 h a s an on-c h ip 5v lo w - dro p re gul ator w i th e x t e rna l ca p a citor to sup p l y the d i gital part of the chi p , some lo w - v o lta g e an alog blocks an d e x terna l circ uitr y . t he voltag e is der ived from an in tern al ba ndg ap refere n c e. t o calcul at e the av ail abl e driv e-curr ent for ext e rna l circu i tr y , the sp ecifie d i l oad shoul d be re duce d w i th the cons um ption of inte rn al circu i tr y (u nl oad ed o u tputs ) and the loa d s conn ected to lo gic outp u ts. see t able 5. 8.8 po w e r-on reset (por) f u n ctio n t he open dra i n outp u t pi n po rb/w d provi d es an ?active l o w ? res e t for e x tern al pur pos es. at po w e r-u p of amis-30 5 22, this pi n w i l l b e kept lo w for s o me time to res e t for e x ampl e an e x terna l mi crocontro ller. a small an al og fi lter avo i ds res e tting due to s p ikes o r nois e o n the vdd supply . t pu t po r t rf pc2007060 4 . 8 vbb v dd h vdd v ddl t pd < t rf t t por/w d pi n f i gure 14: p o wer-on- r e set timing diagram 8 . 9 wa tc hdog fu nc tion t he w a tch d o g function is e n a b le d/disa bl ed t h rou gh bit ( t able 1 4 : spi control r egister w r ). o n ce this bit h a s bee n set to ? 1 ? ( w atc h d og e n a b le), the micr o c ontrol l er n eed s to re- w r i te thi s bit to clear a n inter nal tim e r before th e w a t c hdo g timeo u t interv al ex pi re s. 15 a m i se m i co nd uc t o r ? june 2 007 , m-20684 -001 www.amis.com
AMIS-30522 micro-stepping motor driver data sheet in case th e tim e r is activated and w d e n is ackno w l e dg ed too e a rl y (b efor e t wd p r ) or not w i t h in the inter v al (after t wd t o ), then a reset of the micr ocontr o ller w i ll occur throu g h por b /w d pin. in add ition, a w a rm/cold boot b i t is ava ilab l e in t able 29: spi statu s regist er 0 for further proc essi ng w h en the e x ternal micr oco n troll e r is aliv e aga in. t pu po r/w d pin t por pc 20 07 060 4 . 9 vbb v ddh vdd t t t dsp i enab l e wd ackn owl e dge w d wd tim e r t por t w drd = t wd pr or = t wd to > t wd p r and < t wd t o t t t wd to f i gure 15: w a tchd og timing diagra m note : t d spi is th e time needed by the ex tern al microcontro lle r to shift-in the bit after a po w e r-up. t he duration o f the w a tc hd og timeout interv al is pro g ramm abl e throu gh th e wdt[3:0] bits ( t able 14: spi control r e gister w r ). t h e timing is g i ven in t able 13. table 13: watch dog timeout int e rv al as function of wdt[3.0] index wdt [ 3: 0] t wd t o (ms) 0 0 0 0 0 3 2 1 0 0 0 1 64 2 0 0 1 0 9 6 3 0 0 1 1 128 4 0 1 0 0 1 6 0 5 0 1 0 1 192 6 0 1 1 0 2 2 4 7 0 1 1 1 256 8 1 0 0 0 2 8 8 9 1 0 0 1 320 a 1 0 1 0 3 5 2 b 1 0 1 1 384 c 1 1 0 0 4 1 6 d 1 1 0 1 448 e 1 1 1 0 4 8 0 f 1 1 1 1 512 16 a m i se m i co nd uc t o r ? june 2 007 , m-20684 -001 www.amis.com
AMIS-30522 micro-stepping motor driver data sheet 8.10 clr pin (=hard reset) log ic 0 on c l r pi n al lo w s n o rmal oper atio n of the c h ip. t o reset the compl e te di gita l insi de amis-3 052 2, the i n p u t clr nee ds to be pull ed to lo gic 1 duri ng min i m u m time give n b y t cl r . ( t able 6: ac parame ters ). t h is reset function clear s all inter nal re gisters w i th out the nee d of a po w e r-c y c le. t he op eratio n o f all anal og cir c uits is depe n d in g on the re set state of th e digit a l, charg e pump rem ain s active. log ic 0 on cl r pin res u mes norm a l o perati on a gai n. t he voltage re gul ator rem a in s functio nal du ring an d after t he res e t a nd t he porb/w d pin is n o t activ a ted. w a tchd o g functi on is reset co mp le te ly . 8.11 sleep mo d e t he bit in t able 1 7 : s p i contro l r e g i ster 2 is pr ovid ed to e n ter a s o -call e d ?sle ep mode?. t h is m ode al lo w s re d u ction of c u rre nt- consum ption w hen the mot o r i s not in op erati on. t he effect of sleep mo de i s as follo w s : ? t he drivers are put in hiz ? all an alo g circu i ts are disa ble d and in l o w - p o w e r mod e ? all inter nal re gi sters are maint a ini ng th eir lo gi c content ? nxt and dir i nputs are for b i dde n ? spi communic a tion rem a ins possi ble (sl i ght current incre a s e duri ng spi communic a tio n ) ? reset of chip i s possib l e thro ugh c l r pi n ? oscillator and digit a l clocks are sile nt, ex cept during spi communicati on t he voltag e re gul ator rem a i n s active but w i th red u ce d cur r ent-outp u t ca pab ilit y (i load slp ). t he w a tch d og tim e r stops run n in g and it ?s valu e is kept in the counter. u pon l eavi ng sl e ep mod e , this ti mer contin ues from the value it had bef ore e n terin g slee p mode. normal o per ati on is resume d after w r iti ng lo gic ?0? to bit < slp> . a start-up time is nee ded for the ch arge p u mp to stabiliz e. after thi s time, nxt commands ca n be i ssued. 17 a m i se m i co nd uc t o r ? june 2 007 , m-20684 -001 www.amis.com
AMIS-30522 micro-stepping motor driver data sheet 9.0 spi interf ace t he serial p e ri pher al interfac e (spi) is us ed to a l l o w e x ter nal microc ontr o ller (mcu) to communic a te w i t h th e devic e . t he impl e men t ed spi block is fle x i b le en oug h to interfac e dire ctl y w i t h num er ous microc ontr o llers from sev e ral ma nufactu rers. amis-305 22 acts a lw ay s as a sl ave a n d it can?t i n itiate an y transm i ss ion. t he op era t ion of the dev i c e is co nfi gur e d an d contr o ll e d b y me ans of spi reg isters, w h ich are obs e r vabl e for read and/ or w r ite from the master. 9 . 1 spi tra n s f e r forma t a nd pin signa ls durin g a n spi transfer, data is simultan eo usl y transm i tted ( s hi fted o u t seri all y ) a nd rec e iv ed (shifte d in s e rial l y ). a seria l clock line ( c lk) s y nc hro n izes s h ifting a nd s a mplin g of the i n formatio n on t he t w o s e ria l d a ta l i nes (do and di). do s i gna l is the o u tput from th e s l ave, and di sig nal i s the o u tput from the mast er. a slave s e lec t line ( c sb) al l o w s i ndiv i du al selecti on of a slave spi devi c e in a m ul ti p l e- slave s y stem. t he csb line is active lo w . if amis-3052 2 is not selected, do is in high i m ped ance stat e and it does n o t interfe re w i t h spi bus activities. since ami s -30522 al w a ys clocks data out on the falling edge and samples data in on rising edge of clock, th e m c u spi port must be confi gur ed to match this op eratio n. spi clock idles l o w bet w e e n the trans ferred b y tes. t he diagr am b e lo w is b o th a master an d a s l ave tim i ng di a g ram si nce c l k, do and di pins are dire ctl y c onn ected b e t w e e n the m a st er and the sl ave. 8 7 6 5 4 3 2 1 ms b 6 5 4 3 2 1 ls b ms b 6 5 4 3 2 1 ls b c l k ( i d l es lo w ) d i (f ro m m a s t e r ) do ( f r o m s l a v e ) cs b (1 ) note (1 ): msb of data stored on t he ne w add ress ( s ee transfer packet). the inter nal data-out shift buf fer of amis-3 052 2 is updated w i th ne w content onl y at the last (eve r y eighth) falling edge of the clk sig nal. f i gure 16: timing diagram of an sp i transfer 9.2 t r an sfer pa ck et serial data tran sfer is assume d to follo w ms b first rule. t h e transfer pack e t contains one or more 8-bit c haracters (b yte s ). msb lsb c o mma nd a nd ad d r e ss msb lsb data by te c m d 2 c m d 1 c m d 0 a d d r 4 a d d r 3 a d d r 2 addr1 addr0 data7 - data 0 t he first by te c ontai ns comma nd an d spi reg i ster addr ess a nd w i ll be s ent upfront of the packet to in dic a te to amis-30 522 th e c hos e n register a nd th e t y p e of oper a t ion. t here are t w o possi ble comm ands for the m a ster in norm a l operati on mo d e of amis-305 22: ? read from spi register: cmd2 = 0 ? wri t e to sp i register: cmd2 = 1 18 a m i se m i co nd uc t o r ? june 2 007 , m-20684 -001 www.amis.com
AMIS-30522 micro-stepping motor driver data sheet w r it e command e x ec uted for rea d -o nl y r e gister w i ll n o t affect t he re gis t er an d the d e v ice o per ation. in cas e of re ad comma nd th e data b y te is o p tion al. if a b y te i s transmitted a fter read comm and it is als o interpr e ted as a comman d (see e x am ples b e lo w ) . if the master reads data fr o m a status reg i ster ( spi status re gister d e scripti on ), the n the most si g n ifica n t bit (da t a 7) repr esent s a parit y of data 6 to data 0 b i ts. if the num ber of log i ca l o nes in the d a ta is o dd th en th e p a r i t y bit e q u a ls 1. if the n u mber o f lo gica l o nes is even th en th e parit y b i t equ als 0. t h is is a simple mec h a n ism to protect agai nst no ise and to ver i f y th e correct trans missi on op erati o n and the c onsist enc y of the sta t us data. if a p a rit y check err o r occurs, th e master co uld i n itiate an ad diti ona l rea d co mmand t o o b ta i n the status aga i n . t he csb li ne i s active l o w an d ma y rema in l o w bet w e en e a c h succ essive read c o mma nds. t here is o n l y one e x c epti on of this rul e : if error con d itio n is latche d in status register ( spi status register descri p ti on ) an d the master nee ds to clear the statu s bits then e x a c tl y after read co mmand of a lat c hed status re gister csb li ne shoul d go fro m lo w to hig h . t h is is expl ain ed in the fo llo wing n o te: note: t he stat us reg i sters a n d errb pi n ( s p i status reg i ster descri p tio n ) are updated by the inter n al system clock only w hen cs b line is h i gh. it is recomme n ded to ke ep th e csb lin e hig h alw a ys w hen the spi bus is idle. if the master sends w r it e comman d , then the incom i ng d a ta w i ll b e stored in the corr e s pon din g reg i ster onl y if csb goes from lo w t o hig h . t he w r iti ng to th e re gist er is o n l y en abl ed if e x actl y 16 bits ar e trans mitted w i th in o ne transf e r p a c k et. if more or l e ss clock pulses are cou n ted w i t h in o ne p a cket the compl e te p a cket is ign o re d. amis-3052 2 re spon ds on eve r y inc o min g b y t e b y sh ifting o u t t he data stored on the l a st addr ess s ent vi a the bus. after por the initial addr ess is unk no w n . t he follo w i ng e x amp l es illustrate com m unic a tion ses s ions b e t w e en the master an d AMIS-30522: r ead da t a wr i t e da t a a da t a c da t a b r ead da t a b cs b ma s t e r 305x x a ddr a a ddr b a ddr b a ddr a a dd r b a ddr b las t a d d r d a ta c i s w r i tten i n a d dr b on r i s i ng e dge of c s b r ead a ddr b da t a c a ddr b f i gure 17: e x ample sp i transfer in this exam pl e, the master reads first t he status from addra and then w r ites control b y t e in addrb. after w r ite o pera t ion the master coul d initi a te a read b a ck com m and i n ord e r to verif y the da ta just w r itten. note that the firs t verificatio n read o per ation r eturns the o l d content of addr b, the second r ead comm and returns the n e w ad drb data. note: t he inte rnal data out s h ift buffer of a m is-3052 2 is upd ated w i th the c ontent of t he s e le cte d s p i register on ly at the last (every eig h th) falli ng edg e of the cl k signa l ( spi t r ansfer f o rmat and pin si g nals ). as a result, new data for transmissio n c ann ot be w r itten to the shift buffer at the be gin n in g of the transfer packet and the first b y te shifted out mi ght repr esen t old data. t h is rule also app lies w h en t he master devi c e w a nts to init iate an spi transfer to rea d th e status reg i ste r s. becaus e th e i n ter na l sy stem cl o ck u p d a t e s th e sta t u s reg i ste r s o n ly w hen c sb l i n e i s hig h , th e fi rst rea d o u t by te mig h t rep r e s e n t a n o l d sta t u s (se e fig u r e 18 and f i gure 1 9 ). 19 a m i se m i co nd uc t o r ? june 2 007 , m-20684 -001 www.amis.com
AMIS-30522 micro-stepping motor driver data sheet r ead da t a r ead s t at usa csb ma s t e r 305xx s t at us s t at us s t at us last r ead s t at usa rea d st at u s b s t at us st a t us st a t us s t at us s t at us r egi st er s ar e upd at e d f i gure 18: e x ample sp i transfer t he last case illustrates data poll i n g from se veral re gisters of the spi register bank: cs b r ead r ead r ead ma s t e r a ddr a a ddr b a ddr c da t a da t a a da t a b 305xx a ddr a las t a d d r a ddr b f i gure 19: e x ample sp i transfer 20 a m i se m i co nd uc t o r ? june 2 007 , m-20684 -001 www.amis.com
AMIS-30522 micro-stepping motor driver data sheet 9.3 spi co n t ro l reg i sters all spi control registers h a ve rea d /w rite acce ss and d e fau l t to "0" after po w e r-o n or har d reset. table 14: spi co ntrol register w r con t rol re gist e r (wr) a d d r es s struct ure con t en t bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 access r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 00h data wden wdt[3:0] - - - w here : r/w rea d an d w r ite access reset: status after po w e r-on or har d reset wden : w a tchdog e n a b le. w r iting ?1? to this bit w i ll a c tivate the w a t c hdo g timer (if not ena bl ed ye t) or w i l l clear t h is timer (if alre ad y en ab le d). w r iting ?0? to this bit w i l l cl ear w d bit ( t a ble 2 9 : spi status register 0 ). wdt[3:0] : w a tchdog time out interva l table 15: spi co ntrol register 0 con t rol re gist e r 0 (cr0 ) a d d r es s struct ure con t en t bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 access r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 01h data sm[2:0] cur[4:0] w here : r/w rea d an d w r ite access reset: status after po w e r-on or har d reset sm[2:0] : step mode cur[4:0] : current am plit ude table 16: spi co ntrol register 1 con t rol re gist e r 1 (cr1 ) a d d r es s struct ure con t en t bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 access r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 02h data dirctrl nxtp - - pwmf pwmj emc[1:0] w here : r/w rea d an d w r ite access reset:: status after pow e r-on or hard reset dirctrl directio n contr o l nxtp next polar it y pwmf pw m frequenc y pwmj pwm jitter emc[1:0] emc slop e con t rol table 17: spi co ntrol register 2 con t rol re gist e r 2 (cr2 ) a d d r es s struct ure con t en t bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 access r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 03h data moten slp slag slat - - - - w here : r/w rea d an d w r ite access reset: status after po w e r-on or har d reset moten motor ena bl e slp slee p slag spee d lo ad an gle g a in slat spee d lo ad an gle trans par en c y 21 a m i se m i co nd uc t o r ? june 2 007 , m-20684 -001 www.amis.com
AMIS-30522 micro-stepping motor driver data sheet table 18: spi co ntrol paramete r overvie w slat sy mbo l descrip tion status beha v i or = 0 sla is transpare n t slat speed load angl e transpare n c y bi t = 1 sla is not tra n s parent table 19: spi co ntrol paramete r overvie w slag sy mbo l descrip tion status value = 0 gain = 0.5 slag speed load angl e gain setting = 1 gain = 0.25 table 20: spi pa rameter overvie w pwm f sy mbo l descrip tion status value = 0 f pw m = 22.8khz pwmf enables doubling of the pwm freq uenc y = 1 f pw m = 45.6khz table 21: spi co ntrol paramete r overvie w pwmj sy mbo l descrip tion status beha v i or = 0 jitter disabled pwmj enables jittery p w m = 1 jitter enabled table 22: spi co ntrol overvie w s l p sy mbo l descrip tion status beha v i or = 0 active mode slp enables sleep mode = 1 sleep mode table 23: spi co ntrol paramete r overvie w mote n sy mbo l descrip tion status value = 0 drivers disabled moten activates the motor driver out puts = 1 drivers enabled table 24: spi co ntrol paramete r overvie w dir c t r l sy mbo l descrip tion status value = 0 cw motion = 0 = 1 ccw motion = 0 ccw motion dirct rl controls the dire ction of rotation (in combination w i th logic level on input dir) = 1 = 1 cw motion table 25: spi co ntrol paramete r overvie w nxtp sy mbo l descrip tion status value = 0 trigger on rising edge nxtp selects if nxt triggers on rising o r falling edge = 1 trigger on falling edge cur[4:0] selects imcma x p eak. t h is is the peak or am plitu de of the r egu late d curre nt w a veform in the motor coils. table 26: spi co ntrol paramete r overvie w cu r[4 : 0] index cur[4 : 0] current (m a ) index cur[4 : 0] current (m a ) 0 0 0 0 0 0 3 0 1 0 1 0 0 0 0 3 6 5 1 0 0 0 0 1 60 11 1 0 0 0 1 400 2 0 0 0 1 0 9 0 1 2 1 0 0 1 0 4 4 0 3 0 0 0 1 1 100 13 1 0 0 1 1 485 4 0 0 1 0 0 1 1 0 1 4 1 0 1 0 0 5 3 5 5 0 0 1 0 1 120 15 1 0 1 0 1 595 6 0 0 1 1 0 1 3 5 1 6 1 0 1 1 0 6 5 0 7 0 0 1 1 1 150 17 1 0 1 1 1 725 8 0 1 0 0 0 1 6 0 1 8 1 1 0 0 0 8 0 0 9 0 1 0 0 1 180 19 1 1 0 0 1 885 a 0 1 0 1 0 2 0 0 1 a 1 1 0 1 0 9 7 0 b 0 1 0 1 1 220 1b 1 1 0 1 1 1070 c 0 1 1 0 0 2 4 0 1 c 1 1 1 0 0 1 1 9 0 d 0 1 1 0 1 270 1d 1 1 1 0 1 1300 e 0 1 1 1 0 3 0 0 1 e 1 1 1 1 0 1 4 5 0 f 0 1 1 1 1 325 1f 1 1 1 1 1 1600 22 a m i se m i co nd uc t o r ? june 2 007 , m-20684 -001 www.amis.com
AMIS-30522 micro-stepping motor driver data sheet emc[1:0] adjusts the dv/ d t of the pw m vo ltag e slo pes on the motor p i ns. table 27: spi co ntrol paramete r overvie w emc[1 : 0] index emc[1:0 ] slope (v/ s) remark 0 0 0 150 turn -on and t u rn -off voltage slope 10% to 90 % 1 0 1 100 ? 2 1 0 50 ? 3 1 1 25 ? sm[2:0] selects the mic r o-stepp ing mo de. table 28: spi co ntrol paramete r overvie w sm[2:0 ] index sm[2:0] step mode remark 0 0 0 0 1 / 32 micro-step 1 0 0 1 1 / 16 micro-step 2 0 1 0 1 / 8 micro-step 3 0 1 1 ? micro-step 4 1 0 0 ? uncompensated half-step 5 1 0 1 ? compensated ha lf-step 6 1 1 0 f u ll f u ll step 7 1 1 1 n/a for futu re use 9 . 4 spi sta t us re gis t e r de sc ription all four spi status registers h a ve re ad acce ss and are d e f ault to "0" after po w e r- on or h a rd reset. table 29: spi st atus register 0 status regi ster 0 (sr0) a d d r es s struct ure con t en t bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 access r r r r r r r r reset 0 0 0 0 0 0 0 0 04h data par tw cpfail wd (1) openx openy - - w here : r read only mode access reset status after po w e r-on or hard reset par parit y check tw t hermal w a r n i ng cpfail char ge pum p failur e wd w a tchdog ev e n t openx open co il x de tected openy open co il y de tected remark : wd (1 ) ? t h is bit in dic a tes that the w a tchdo g timer has n o t be en c l ear ed pr op erl y . if the master reads th at w d i s set to ?1? afte r reset, it means that a w a tc hd og reset occ u rr ed ( w arm b oot ) instead of por (cold bo ot). w d bit w i l l b e clear ed o n l y w hen the master w r ites ?0? to wden bit. t a b l e 14: spi cont rol re gister w r . data is not latched 23 a m i se m i co nd uc t o r ? june 2 007 , m-20684 -001 www.amis.com
AMIS-30522 micro-stepping motor driver data sheet table 30: spi st atus register 1 status regi ster 1 (sr1) a d d r es s struct ure con t en t bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 access r r r r r r r r reset 0 0 0 0 0 0 0 0 05h data par ovcxpt ovcxpb ovcxnt ovcxnb - - - w here : r read only mode access reset status after po w e r-on or hard reset par parit y check ovxpt over-current d e tected o n x h - bridg e : mot xp terminal, top transistor ovxpb over-current d e tected o n x h - bridg e : mot xp terminal, bott o m transistor ovxnt over-current d e tected o n x h - bridg e : mot x n terminal, top transistor ovxnb over-current d e tected o n x h - brid ge: mo t x n terminal, bottom transistor remark : data is latched table 31: spi st atus register 2 status regi ster 2 (sr2) a d d r es s struct ure con t en t bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 access r r r r r r r r reset 0 0 0 0 0 0 0 0 06h data par ovcypt ovcypb ovcyynt ovcynb tsd - - w here : r read only mode access reset status after po w e r-on or hard reset par parit y check ovcypt over-current d e tected o n y h-brid ge: mo t yp terminal, top transistor ovcypb over-current d e tected o n y h-brid ge: mo t yp terminal, bott o m transistor ovcynt over-current d e tected o n y h-bridg e : mot y n terminal, top transistor ovcynb over-current d e tected o n y h-brid ge: mo t y n terminal, bottom transistor tsd t hermal shutd o w n remark : data is latched table 32: spi st atus register 3 status regi ster 3 (sr3) a d d r es s struct ure con t en t bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 access r r r r r r r r reset 0 0 0 0 0 0 0 0 07h data par msp[6:0] w here : r read only mode access reset status after po w e r-on or hard reset par parit y check msp[6:0] t r anslator micro-step pos itio n remark : da ta is not latched 24 a m i se m i co nd uc t o r ? june 2 007 , m-20684 -001 www.amis.com
AMIS-30522 micro-stepping motor driver data sheet table 33: spi st atus flags overv i ew flag mnem onic leng th (bit ) relate d spi reg i ster com m en t reset s t ate charge p u mp failure cpfail 1 status registe r 0 ?0? = no failur e ?1? = fa ilure: indicates that the charge pump does not reach the req u ired voltage level. note 1 ?0? micro-step position msp[6:0] 7 status registe r 3 translator micro step position ?0000000? o pen coil x openx 1 status registe r 0 ?1? = open coil detected ?0? o pen coil y openy 1 status registe r 0 ?1? = open coil detected ?0? ov er c urr ent on x h-bridge; m o t xn terminal; b ottom tran. ovcxnb 1 status registe r 1 ?0? = no failur e ?1? = failure: indicates that o v er current i s detected at botto m transistor xn-t erminal ?0? ov er c urr ent on x h-bridge; m o t xn terminal; t op t r a n sist. ovcxnt 1 status registe r 1 ?0? = no failur e ?1? = failure: indicates that o v er current i s detected at top t r ansistor xn-term i nal ?0? ov er c urr ent on x h-bridge; m o t xp terminal; b ottom tran. ovcxpb 1 status registe r 1 ?0? = no failur e ?1? = failure: indicates that o v er current i s detected at botto m transistor xp-t e rminal ?0? ov er c urr ent on x h-bridge; m o t xp terminal; t op t r a n sist. ovcxpt 1 status registe r 1 ?0? = no failur e ?1? = failure: indicates that o v er current i s detected at top t r ansistor xp-terminal ?0? ov er c urr ent on y h-bridge; m o t yn terminal; b ottom tran. ovcynb 1 status registe r 2 ?0? = no failur e ?1? = failure: indicates that o v er current i s detected at botto m transistor y n -t erminal ?0? ov er c urr ent on y h-bridge; m o t yn terminal; t op t r a n sist. ovcynt 1 status registe r 2 ?0? = no failur e ?1? = failure: indicates that o v er current i s detected at top t r ansistor y n - t erm i nal ?0? ov er c urr ent on y h-bridge; m o t yp terminal; b ottom tran. ovcypb 1 status registe r 2 ?0? = no failur e ?1? = failure: indicates that o v er current i s detected at botto m transistor y p -t erminal ?0? ov er c urr ent on y h-bridge; m o t yp terminal; t op t r a n sist. ovcypt 1 status registe r 2 ?0? = no failur e ?1? = failure: indicates that o v er current i s detected at top t r ansistor y p -te r minal ?0? thermal shutdo w n tsd 1 status registe r 2 ?0? t her mal w a r n ing tw 1 status registe r 0 ?0? watchdog event wd 1 status registe r 0 ?1? = w a tchdog re set after time-out ?0? 25 a m i se m i co nd uc t o r ? june 2 007 , m-20684 -001 www.amis.com
AMIS-30522 micro-stepping motor driver data sheet 10.0 pack age outline dimensions: dim min nom max unit a 0 . 8 0 . 9 m m a 1 0 0 . 0 2 0 . 0 5 m m a 2 0 . 5 7 6 0 . 6 1 5 0 . 6 5 4 m m a 3 0 . 2 0 3 m m b 0 . 2 5 0 . 3 0 . 3 5 m m c 0 . 2 4 0 . 4 2 0 . 6 m m d 7 m m d 1 6 . 7 5 m m e 7 m m e 1 6 . 7 5 m m e 0 . 6 5 m m j 5 . 3 7 5 . 4 7 5 . 5 7 m m k 5 . 3 7 5 . 4 7 5 . 5 7 m m l 0 . 3 5 0 . 4 0 . 4 5 m m p 4 5 d e g r e e r 2 . 1 8 5 2 . 3 8 5 m m notes : 2 dimensions apply to plated te rmi nal and are mea s ured bet w e en 0 . 2 and 0.25 mm from t e r m inal tip. 3 the pin #1 indication must be placed on the top surface of the pa ckage b y using indentat ion mark or othe r feature of package bod y. 4 exact shape an d size of this feat ure is optional 5 applied for exposed pad and termi nals. excl ude embe dding part of exposed pa d fro m measuring. 6 applied only to t e rminals 7 exact shape of each corner is op tional 7x7 nqf p f i gure 20: nqf p -32: no lead quad f l at p a ck; 32 p i n s ; b ody size 7x7mm ( a mi s reference: nqf p - 32) 26 a m i se m i co nd uc t o r ? june 2 007 , m-20684 -001 www.amis.com
AMIS-30522 micro-stepping motor driver data sheet 11.0 soldering 11.1 introduction t o sold ering s u rface mount packages t h is text g i ves a v e r y brief in sight to a com p le x tech nol og y. a more i n -d epth acco unt o f sold erin g ics can b e fo und i n the amis ?dat a han dbo ok ic2 6 ; integrate d c i rcuit pack ages ? (docum ent or der n u mber 93 98 6 52 90 011). t here is no s o ld erin g meth o d that is i d e a l for all surface mo unt ic pack a g e s. w a ve s o l d erin g is n o t a l w a ys s u it ab le for surfac e m o unt ics, or for printe d-circu i t boar ds (pcb) wi t h hig h po pul atio n densiti e s. in these situat i ons r e -flo w so lder in g is often use d . 11.2 re-flo w so ld erin g re-flo w sol der i ng re qu ires s o lder paste (a s u spe n sio n of fine s o ld er p a rti c les, flu x an d bin d in g a g e n t) to be a ppl ied to the p c b b y screen pr inti n g , stencill in g or pressur e -s yring e disp ens i ng bef or e p a c k age p l ac eme n t. several m e thods e x ist for re-flo w i ng; for examp l e, infrar ed/conv ectio n heat i ng i n a co nve y or t y pe ov en. t h roughp ut times (pre he atin g, sold eri ng an d cooli ng) var y b e t w e e n 1 00 an d 2 00 s e con d s dep en din g o n t he heati ng m e t hod. t y p i cal re- flo w pe ak temp eratures ra ng e from 215 to 26 0c. t he top-surface temper a t ure of the pac kages sh ou ld p r eferab l y be ke pt belo w 23 0 c. 11.3 w a v e so ld erin g conv entio na l singl e w a v e sol deri ng is not re commen ded fo r surface m oun t devices (smd s) or pcbs w i t h a hig h comp one nt dens it y , a s sold er bri d g i ng and no n- w e tti ng ca n pr ese n t major pr ob le ms. t o overco me these pro b l ems, the dou b l e- w a v e so ld eri ng meth od w a s specific all y d e v e lo ped. if w a ve so lder i ng is use d the follo w i n g con d iti ons must be o b serve d for opt imal resu lts: ? use a do ub le- w a v e so lder in g method compr i sing a turbul en t w a v e w i t h hi g h up w a rd pr essure foll o w e d b y a smo o th lam i nar w a ve. ? f o r packag e s w i t h le ads o n tw o s i d e s an d a pitch (e): ? larg e r than or equ al to 1.27m m, the footprint long itudi na l a x is is preferre d to be par all e l to the transport d i rectio n of the p cb; ? smaller th an 1 . 27mm, the footprint lon g itu d i nal a x is must be par all e l to the transp o rt di rection of the pcb. t he footprint must incor porate so l der thiev e s at the do w n stre a m end. ? f o r packa ges w i t h l eads on four sid e s, th e footprint m u st be p l ac ed at a 45o ang le to the trans port directi on of th e pcb. t h e footprint must i n corp orate sol der thiev e s do w n stream a nd at the side cor ners. durin g pl acem ent and b e fore solderi ng, t he packa ge must be fixed w i t h a dropl et of adh esive. t he adh esive ca n be a ppli ed b y scr een printi ng, p i n tra n sfer or s y rin g e d i spe n si ng. t he pack age ca n b e s o ld ered after the ad hes ive is cur ed. t y pical d w e l l tim e is fo ur sec o n d s at 250c. a mil d l y -activ ated fl ux w i ll e limi nat e the ne ed for remova l of corrosive res i du es in most app lica t ions. 1 1 . 4 ma nua l sol d e r ing f i x the com p o nent b y first sol deri ng t w o d i ag ona ll y-o p p o site end le ads. us e a lo w vo ltag e (24v or less) s o ld erin g iro n a ppli ed to the flat part of the lea d . contact time must be limite d to 10 secon d s at up to 300 c. w hen usi ng a ded icate d tool, all oth e r lea d s can be so ld ere d in on e op erat ion w i t h in t w o t o five secon d s bet w e en 2 70 a nd 32 0c. table 34: solderi ng process solderin g met h od package wav e re-fl o w (1 ) bg a, sqfp not suitable suitable hlqfp, hs q f p, hso p , htssop, sms not suitable (2 ) suitable plcc (3 ) , so, s o j suitable suitable lqfp, qfp, t q fp n o t r e co m m e n ded (3 ) (4 ) suitable sso p, tss o p, vso not recommend e d (5 ) suitable notes: (1) all s u r f a c e m ount ( s m d ) pac k a ges a r e m o is t u re s e n s i t iv e. depending upo n t he m o ist u re c o n t e n t , t he m a x i m u m t e m perat ure (w it h re spec t t o t i m e ) and b ody s i z e of t he pa c k a ge, t h e r e is a risk t h a t int e rnal or ex t e rnal pack age c r acks m a y oc c u r due t o v aporiz at ion of t he m o ist u r e in t hem (t he s o called popc or n ef fect ). for det ail s , re f e r t o t he dry pac k in f o rm a t ion in t h e ?data handb ook i c 26 ; i n t egra t e d circ u i t pa c k a ges; se c t ion : pa c k i n g m e t hod s . ? (2) thes e pa c k a ges a r e not s u itable for wav e s o ldering as a s o lder jo int be t w een t he pcb and hea t s in k (a t bo t t om v e r s ion) c an n o t be a c hiev ed, and as s o ld er m a y s t i c k t o t h e hea ts in k ( on t o p v e rs ion). (3) i f w a v e s o ldering i s c o n s ide r ed, t hen t he pack age m u s t be pl ac ed a t a 45 angle t o t he s o l d er w a v e direc t ion. the pac k a ge f oo t p rint m u st in c o rpora t e s o ld er t h iev e s dow ns t r ea m and a t t h e s i de corners. (4) wav e s o ldering is only s u it able f o r lq fp, tqfp and qf p pack age s w i t h a pit c h (e) equ al t o o r larger than 0.8m m ; it i s de f i n i t ely not s u itable f o r pa c k ag es w i t h a pit c h (e ) eq ual t o or s m alle r t han 0.65 m m . (5) wav e s o ldering i s only s u it able for s s op and tsso p pack age s w i t h a pitc h (e) eq ual t o or l a rger t h a n 0. 6 5 m m ; it i s de f i ni t e ly not s u itable for pa c k a g e s w i t h a pit c h (e ) eq ual t o or s m alle r t han 0.5m m . 27 a m i se m i co nd uc t o r ? june 2 007 , m-20684 -001 www.amis.com
AMIS-30522 micro-stepping motor driver data sheet 12.0 company or product inquiries f o r more infor m ation a b o u t ami semicond u c tor?s prod ucts or services visit our web site at http:// w w w . amis.com. 13.0 documen t h i s t o r y table 35: revision histor y version date modifi cati on 0 . 1 1 8 - j a n - 0 6 i n i t i a l d r a f t 0.2 24-jan-06 draft : changed pwm description, added sla pin d e scription, changed por a nd wd paragr aphs. 0.3 9-feb-0 6 cen->cenb, n x t pin timing, spi i/f, 30522 sec t ion 8.5, 8.6,8.7, 30522 section 8.4,8.5 0.4 9-mar - 06 updated pin-o u t & added dra w i n g , cenb->clr , e rr- >errb, rem o ved swp bits, updated spi bits, added package details 0.5 22-mar - 06 renamed cs -> csb, swapped p i ns clr and cs b 0.6 24-ma y-06 updated pins, a c &dc tables, sl a specs, sm[2:0] decoding 1.0 6-june-07 final version deriv ed from commo n 30521/305 22 d a tasheet dev i c e s s o ld by am i s are cov e red by t he w a rrant y and pat en t indem ni f i c a t i on prov is ions appe aring in its term s o f sale only . am i s m a k e s no w a rrant y , ex pres s, st atut ory , im plied or by des c r i p t i on , rega rding t h e inf o rm a t ion s e t f o r t h herein or r egardi ng t h e freedom o f the de s c r i bed dev ices f r om pa t e n t in f r i ngem ent. am i s m a k e s no w a rrant y of m e rc han t abili t y or f i t n e s s for any purp o s e s . am i s re s e r v es t he right t o di sc ontinue produ c t io n and c hange s p e c if i c a t ion s and p rices at any t i m e and w i t hout no t i c e . am i sem i c ondu ct or's pr oduct s are i n t end e d f o r use in c o m m e rc ial appli c at i ons. applic a t ion s r equiri ng ex t ended tem p e r at ure range , u nu sual env ironm ent al r equirem ents, or hig h reliabilit y applica t io ns, such as m ilit a r y , m edical lif e-sup p o rt or lif e- su stainin g equipm ent, are speci f ica lly not recom m ended w i t hout addit i ona l proc e s s i ng by am i s f o r s u c h applic a t ion s . copyright ?2007 am i se m i c ondu c t o r , i n c. 28 a m i se m i co nd uc t o r ? june 2 007 , m-20684 -001 www.amis.com

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